1. Field of the Invention
The present invention relates to a display driving control technology, and more particularly, to a driving control technology with power-saving function.
2. Description of Related Art
With the development of technology, displays have been very widely used. Based on the persistence of vision, when the display consecutively updates the images of the display panel such that more than twenty-four frames are presented per second, the human eye will be given an illusion that the displayed images are animated images. The time for the display to present one frame is usually referred to as one frame time, which is about 16.6 ms. The operation of the display to display the frames is further described below.
FIG. 1 illustrates conventional frame times in relation to the displaying control mode of a liquid crystal display (LCD). FIG. 2 illustrates the configuration of a conventional LCD. Operation of the LCD 10 to display frames is described below with reference to FIGS. 1 and 2. First, the image information of the frame 100 is transmitted from a timing controller 20 to a display data memory 30 according to timing. Then, the image information of the frame 100 stored in the display data memory 30 is converted into an analog voltage by a digital to analog converter 40. The analog voltage is then transmitted to corresponding transistors (not shown) of a display panel 60 by a source buffer 50.
During the period of displaying the frame 100 by the LCD 10, the timing controller 20 may also output a timing control signal to a gate buffer 70 to enable the gate buffer 70 to timely turn on the corresponding transistors (not shown) of the display panel 60. In addition, the timing controller 20 may also output a timing control signal to a common electrode buffer 80 to enable the common electrode buffer 80 to provide positive or negative common electrode voltage to the display panel 60. Operation of the LCD 10 to display other frames (i.e., frame 101 or the like) may be substantially the same as those described above and is therefore not repeated herein.
It should be noted that, during the period of displaying each frame, the LCD 10 is constantly in a displaying mode. In the displaying mode, all of the memory voltage VSRAM, digital to analog converting voltage VDAC, source voltage VSP, common electrode high voltage VCOMH, common electrode low voltage VCOML, gate high voltage VGH and gate low voltage VGL are maintained at a fixed value. Furthermore, the oscillation frequency of the oscillator (not shown) inside the timing controller 20 is maintained at a fixed value. In other words, the conventional LCD 10 does not have a power-saving function during the displaying period of each frame.